TITLE "OCXO Synchronizer rel.2.0 mar 20,2013"; SUBDESIGN ocxo_pll -- R R R R R -- E E E E E -- S S S V S S -- E E E C v r E E -- R R R C x e R R -- V V V I o G G f G V V -- E E E N i N N i N E E -- D D D T n D D n D D D -- -----------------------------------_ -- / 44 43 42 41 40 39 38 37 36 35 34 | -- #TDI | 1 33 | RESERVED -- | 2 32 | #TDO -- | 3 31 | RESERVED -- GND | 4 30 | GND --RESERVED | 5 29 | VCCIO --RESERVED | 6 EPM3032ATC44-4 28 | RESERVED -- #TMS | 7 27 | RESERVED --RESERVED | 8 26 | #TCK -- VCCIO | 9 25 | RESERVED --RESERVED | 10 24 | GND -- GND | 11 23 | conf_2 -- |_ 12 13 14 15 16 17 18 19 20 21 22 _| -- ------------------------------------ -- l r p c G V c c c c v -- d e d h N C h h h o x -- 1 f 1 k D C k k k n o -- o 0 I 1 2 3 f p -- u N _ o -- t T 0 l -- -- VXO IN : 100MHz input -- ref in : external reference ( --conf[2..0], vxoin, refin, vxopol : INPUT; vxoout, refout, chk[1..0], --pd2n, --pd2i, ld1, pd1 : OUTPUT; ) VARIABLE -- refcount[3..0] :DFF; -- refzero :SOFT; lockdet :SOFT; vxocount[7..0] :DFF; vxozero :SOFT; refdiv :DFF; vxodiv :DFF; refdiv2 :DFF; vxodiv2 :DFF; vxo_n[3..0] :SOFT; -- ref_n[3..0] :SOFT; BEGIN vxo_n[] = 9; --VXO=100MHz -- ref_n[] = 2; --REF=10MHz chk0 = vxo_n0; chk1 = vxo_n1; --chk2 = ref_n6; --chk3 = ref_n7; --------REF programable divider------------- -- refcount[].clk = refin; -- refzero = !refcount0.q -- & !refcount1.q -- & !refcount2.q -- & !refcount3.q; -- IF refzero THEN -- refcount[].d = ref_n[]; -- ELSE -- refcount[].d = refcount[].q - 1; -- END IF; --------VXO programable divider------------- vxocount[].clk = vxoin; vxozero = !vxocount0.q & !vxocount1.q & !vxocount2.q & !vxocount3.q; -- & !vxocount4.q -- & !vxocount5.q -- & !vxocount6.q -- & !vxocount7.q; IF vxozero THEN vxocount[].d = vxo_n[]; ELSE vxocount[].d = vxocount[].q - 1; END IF; -----phase detector--------------------- vxodiv.clk = vxozero; vxodiv2.clk = vxozero; vxodiv.d = !vxodiv2.q; --make duty 50percents vxodiv2.d = vxodiv.q; -- refdiv.clk = refzero; -- refdiv2.clk = refzero; refdiv.clk = refin; refdiv2.clk = refin; refdiv.d = !refdiv2.q; refdiv2.d = refdiv.q; pd1 = refdiv2.q xor vxodiv2.q; lockdet = refdiv2.q xor vxodiv.q; ld1 = !(lockdet xor vxopol); ------ frequency monitor---------------- refout = refdiv2.q; vxoout = vxodiv2.q; END;